1. Technical Field
The present disclosure relates to a semiconductor memory device and, more particularly, to non-vola tile memory device capable of reducing threshold voltage distribution.
2. Discussion of the Related Art
A flash memory device is a kind of EEPROM where a plurality of memory regions called cells can be erased or programmed through a single program operation. A conventional EEPROM enables only one memory region to be erased or programmed at one time. This means that a flash memory device can operate at a higher and more effective speed. After a specific number of erase operations, all types of flash memories and EEPROM may wear out due to a breakdown of an insulating layer covering charge storage means used to store data.
A flash memory device stores information in such a manner that a power supply voltage is not required to keep information stored in the silicon chip. This means that information is kept without power consumption even if a power supply voltage applied to a chip is cut off. In addition, a flash memory device can resist physical impact and achieve fast read access time, especially when compared to a hard disk drive. For these characteristics, flash memory devices have been used as storage for devices that are powered by a battery. A flash memory device is classified into two groups, e.g., a NOR flash memory device and a NAND flash memory device according to a configuration of a logic gate used in each of storage devices.
A flash memory device stores information in an array of transistors called “cells,” and each of the cells conventionally stores 1-bit of information. More advanced flash memory devices called “multi-level devices” can store more than 1-bit per cell by varying a charge amount on a floating gate of each cell.
In a NOR flash memory device, each cell is similar to a standard metal-oxide-semiconductor field-effect transistor (MOSFET) except that it has two gates. The first gate is a control gate analogous to those in MOS transistors, while the second gate is a floating gate surrounded by an insulating film. The floating gate is placed between the control gate and a substrate (or bulk). Since the floating gate is insulated by an insulating film, electrons on the floating gate are trapped, thus storing information. When electrons are placed on the floating gate, an electric field from the control gate is changed (partially countervailed) by electrons, which affects a threshold voltage of the memory cell. Accordingly, when a cell is read by applying a specific voltage to the control gate, current flows or does not flow according to a threshold voltage of a cell. This is controlled by a charge amount of the floating gate. The current is analyzed and, in the 1-bit cell, whether a current is sensed determines the state of the cell. The state of the cell is determined to be either 1 (unprogrammed) or 0 (programmed). Accordingly, stored data is reproduced in a multi-level cell device storing more than 1-bit per cell, in order to determine an electron amount stored in the floating gate, the amount of current flowing may be sensed, rather than sensing whether current flows.
A NOR flash cell is programmed by applying a program voltage to a control gate and a high voltage of, for example, 5V to 6V to a drain, with a source being grounded. According to this bias condition, current flows from the drain to the source. This programming manner is called hot-electron injection. In order to erase the NOR flash cell, a large voltage difference is forced between a control gate and a substrate (or bulk), which enables electrons to be discharged from a floating gate through F-N tunneling. In general, constituent elements of a NOR flash memory device are divided into erase segments called blocks or sectors. Memory cells in a sector all are erased at the same time. However, NOR programming can be carried out in a byte or word unit.
After a program operation is carried out, it is judged whether a memory cell is programmed to have a desired data value. This operation is referred to as a verify operation (or, a verify read operation). In general, a program operation and a verify operation constitute a loop (cycle), which may be repeated within a predetermined number of times. For example, after a memory cell is programmed, with a verify read voltage being applied to a selected word line, whether a threshold voltage of the programmed memory cell is higher than the verify read voltage is judged. If a threshold voltage of the programmed memory cell is higher than the verify read voltage, a program operation for the memory cell (marked by “10” in FIG. 1) is not performed in a next loop. Afterwards, this memory cell may be called a program end cell. On the other hand, if a threshold voltage of the programmed memory cell is lower than the verify read voltage, a program operation for the memory cell (marked by “11” in FIG. 1) is performed in a next loop. The number of program end cells may increase gradually according to repetition of program loops. For example, as illustrated in FIG. 2, the number of cells to be programmed may decrease gradually according to repetition of program loops.
A current or drain current flowing via a memory cell may be changed as a read operation is repeated. A variation of a drain current means a variation of a threshold voltage. In general, this phenomenon is called random telegraph noise (RTN). The RTN may have various causes. Typically, such a problem may be caused by a charge trapped at an insulation film between a floating gate (or a charge trap gate) and a substrate. Although a threshold voltage (marked by “20” in FIG. 3) of a memory cell is judged to be higher than a verify read voltage at a verify read operation, as illustrated in FIG. 3, a threshold voltage (marked by “21” in FIG. 3) of the memory cell is judged to be lower than the verify read voltage. This is because a threshold voltage of a memory cell is changed due to the above-described RTN.
In particular, as illustrated in FIG. 4, threshold voltages of memory cells placed at a lower/tail portion of a threshold voltage distribution are substantially varied due to an iterative read operation, while threshold voltages of memory cells placed at a center portion of a threshold voltage distribution are slightly varied due to an iterative read operation. As threshold voltages of memory cells placed at a lower/tail portion of a threshold voltage distribution are substantially varied, a read margin may be reduced. As a result, read errors may be generated and a threshold voltage distribution may be widened. Further, as illustrated in FIG. 5 showing a threshold voltage variation according to technology scaling, a variation of a threshold voltage due to the RTN may increase according to the technology scaling. In particular, a variation of a threshold voltage due to the RTN may cause substantial error in a multi-bit flash memory device where margin between states is less.